Chelsea Search Group, Inc.
Senior Static Timing Analysis (STA) Engineer
Chelsea Search Group, Inc., Austin, Texas, us, 78716
Senior STA Engineer
Austin, Texas (onsite/hybrid)US Citizen or US Permanent Resident6-12 months contract with possible extensions
Required Skills & Experience
7+ years of experience in Static Timing AnalysisDemonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designsUnderstand crosstalk, noise, OCV, timing marginsFamiliarity with Clock specs, jitter, IR drop, spice analysisWorking with multi-site teams for executionWork with methodology teams to constantly improve flows and processesExperience with STA Lead roles a plusExpertise in developing, implementing, and verifying STA constraintsExpertise in efficient closure of Subsystem as well as SoC-level timing including running optimization on PTECO for timing and PowerKnowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & RouteKnowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixesContribute to timing flow and methodology improvementsBSEE required
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Austin, Texas (onsite/hybrid)US Citizen or US Permanent Resident6-12 months contract with possible extensions
Required Skills & Experience
7+ years of experience in Static Timing AnalysisDemonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designsUnderstand crosstalk, noise, OCV, timing marginsFamiliarity with Clock specs, jitter, IR drop, spice analysisWorking with multi-site teams for executionWork with methodology teams to constantly improve flows and processesExperience with STA Lead roles a plusExpertise in developing, implementing, and verifying STA constraintsExpertise in efficient closure of Subsystem as well as SoC-level timing including running optimization on PTECO for timing and PowerKnowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & RouteKnowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixesContribute to timing flow and methodology improvementsBSEE required
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