Senior Digital IC Design Engineer - Power Management

Job Type: Full-TimeLocation: MN - Bloomington, USRequisition ID: 5781Summary:Qorvo is seeking a Digital Design Engineer responsible for a wide variety of Digital ASIC Design tasks. Designs primarily interface to Analog Power Solutions, including development of State Machines, Serial Interfaces, Register Blocks, OTP Blocks, supporting Clock and Reset analog circuits, and timed enabling/switching of Analog signal paths. This position involves the full Digital Design flow including interacting with Systems for Specification generation, Architecture development, RTL description using System Verilog, Verilog Simulation Verification via developed Test Benches, Logic Synthesis, executing a Place & Route tool and associated Static Timing Analysis, and familiarization with Scan testing. Documentation and presentation at Design Reviews is required.Responsibilities:Receive Specifications from Module Architects / System Engineers – review, assess, provide feedback, and develop a digital micro-architectureGenerate RTL to comply with specifications, both by manual development and automated generationCreate Cadence schematic database of Digital Blocks via VirtuosoSystem Verilog Verification Simulations of the design by creating Test Benches at block level. Create new Verification tests and utilize existing tests that are to be modified as needed. Execute both RTL and Gate Simulations.Execute Logic SynthesisCreate DFT hooks and generate test patternsExecute remaining back-end tools – Place & Route/Static Timing Analysis, LEC, LINT, CDC, ATPGQualifications:System Verilog / Verilog Language and SimulationScripting languages (Python, TCL, UNIX/LINUX, shell, PERL, C/C++)Synthesis and Static Timing AnalysisStrong communication skills to interface with other teamsBSEE required, MSEE preferredPlace & Route using Cadence Virtuoso, verifying Database vs SchematicsSystem Verilog Assertions and Functional Coverage

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