Sr. Digital Design Engineer

Job Duties:Conduct image sensor array/analog related timing control design and Image Signal Processing (ISP) system level integration using Verilog and Python.Perform chip level architecture definition, including analog interface/control, image data processing, ISP datapath, power, performance, and area trade-offs.Integrate and validate ISP data pipes according to PRD/design specification & system architecture of SoC CIS products.Perform full-chip integration and verification using SimVision, Verdi, SystemVerilog and Perl.Perform logic synthesis, logic equivalence checking, static timing analysis and power analysis.Perform chip bring-up, validation, and debugging using FPGA and Python.Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.Develop ISP functions, such as PD Compensation and AWB Gain, for timing and power consumption optimization by using High Level Synthesis with Siemens Catapult.Perform RTL coding, function/performance simulation debug, Lint/CDC/FV/UPF checks.Conduct synthesis design with Cadence RCC or Genus.Participate in timing/power closure and FPGA/silicon bring-up.Participate in test plan and coverage analysis of the block and SOC-level verification.Finish RTL coding of functional blocks in design to meet full-chip integration target time.Work with CIS project lead, sensor digital and analog engineers for system integration & validation.Work with back-end team closely in floor planning, timing closure, and DFT.Work with algorithm and application engineers for image tuning and qualification by using MATLAB, C and C++.Requirements:Master’s degree in Electrical Engineering, Electronics Engineering, or a related field. Will accept foreign equivalent Master’s degree.Plus two (2) years of work or research experience as an engineer, graduate assistant, or researcher with the following skills/experience:Circuit analysis for DC and AC circuits;Circuit verification;Digital Circuit applications;Electrical Circuit and Digital Circuit design;Reading schematics for Electrical Circuit and Digital Circuit;Circuit debugging;MATLAB, C, C++, Verilog;Lab test equipment, oscilloscopes, power suppliers and multi-meters.Annual base salary for this role in California, US is expected to be between $126,984 - $130,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

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