ESR Healthcare
Camera design engnr python San Jose Toronto
ESR Healthcare, San Jose, California, United States, 95199
Experience level:
Mid-senior
Experience required:
5 Years
Education level:
Bachelor’s degree
Job function:
Information Technology
Industry:
Information Technology and Services
Compensation:
View salary
Total position:
5
Relocation assistance:
Yes
Visa:
Only US citizens and Greencard holders
Job Responsibilities:
Develop test strategies to verify next generation camera processors.
Develop and review block and chip level verification environments and test plans.
Work closely with design engineers to develop test benches and test plans to meet coverage goals.
Participate in selecting best in class 3rd party protocol verification IP.
Help enhance the overall DV methodology by analyzing 3rd party verification tools.
Debug failures in simulation and collaborate with designers in identifying root-cause issues.
Develop tests that will help achieve functional safety goals that meet ISO26262 compliance.
Work with the systems and software teams on emulation platforms.
Participate in the bring-up and debug of the device prototype.
Provide support to the Product Engineering team to meet all validation and qualification goals for the product.
Minimum Qualifications:
BSEE/BSCE/BSCS.
5 years of industry experience in design verification.
Experience with test planning, test bench architecture and assertions.
Constrained random verification experience with SystemVerilog using UVM.
Coverage driven verification (code/functional/assertion coverage).
Strong programming skills in C/C++ and scripting experience with Python/Tcl/Perl.
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Mid-senior
Experience required:
5 Years
Education level:
Bachelor’s degree
Job function:
Information Technology
Industry:
Information Technology and Services
Compensation:
View salary
Total position:
5
Relocation assistance:
Yes
Visa:
Only US citizens and Greencard holders
Job Responsibilities:
Develop test strategies to verify next generation camera processors.
Develop and review block and chip level verification environments and test plans.
Work closely with design engineers to develop test benches and test plans to meet coverage goals.
Participate in selecting best in class 3rd party protocol verification IP.
Help enhance the overall DV methodology by analyzing 3rd party verification tools.
Debug failures in simulation and collaborate with designers in identifying root-cause issues.
Develop tests that will help achieve functional safety goals that meet ISO26262 compliance.
Work with the systems and software teams on emulation platforms.
Participate in the bring-up and debug of the device prototype.
Provide support to the Product Engineering team to meet all validation and qualification goals for the product.
Minimum Qualifications:
BSEE/BSCE/BSCS.
5 years of industry experience in design verification.
Experience with test planning, test bench architecture and assertions.
Constrained random verification experience with SystemVerilog using UVM.
Coverage driven verification (code/functional/assertion coverage).
Strong programming skills in C/C++ and scripting experience with Python/Tcl/Perl.
#J-18808-Ljbffr