Microsoft
Principal Logic Design Manager
Microsoft, Austin, Texas, us, 78716
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.
We are looking for a
Principal Logic Design Manager
to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a self-starter who will thrive in this cutting-edge technical environment.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.
Responsibilities
The AISoC silicon team is seeking a passionate and intellectually curious Principal Logic Design Manager to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. In this role you will:Build, hire, and mentor a team of talented engineers, supporting their career growth and professional development.Manage a logic design team for the development of custom IP and Subsystem (SS) components with focus on architectural and micro-architectural based functions and features.Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP.Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design.Provide technical leadership through mentorship and teamwork.Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.Embody our Culture and Values.Qualifications
Required Qualifications:
9+ years of related technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience.8+ years experience in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.7+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug.3+ years managing logic design teams.Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings. Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.Preferred Qualifications
15+ years of experience in logic design delivering complex solutions.10+ years of experience in one or more of the following – floating point arithmetic and datapath design, Direct Memory Access(DMA) design, subsystem designs/integration, or custom logic design.5+ years of experience managing and leading logic design teams.Multiple successful Application specific Integrated Circuit(ASIC) tape outs in deep sub-micron technologies.Experience with scripting language such as Python or Perl.Experience debugging designs as well as simulation environment.Knowledge of verification principles, testbenches, Universal Verification Methodology(UVM), and coverage.Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs.Working knowledge of writing assertions, coverage and formal verification.Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
Microsoft Careers .Microsoft will accept applications for the role until May 27, 2024.Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
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We are looking for a
Principal Logic Design Manager
to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a self-starter who will thrive in this cutting-edge technical environment.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.
Responsibilities
The AISoC silicon team is seeking a passionate and intellectually curious Principal Logic Design Manager to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. In this role you will:Build, hire, and mentor a team of talented engineers, supporting their career growth and professional development.Manage a logic design team for the development of custom IP and Subsystem (SS) components with focus on architectural and micro-architectural based functions and features.Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP.Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design.Provide technical leadership through mentorship and teamwork.Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.Embody our Culture and Values.Qualifications
Required Qualifications:
9+ years of related technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience.8+ years experience in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.7+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug.3+ years managing logic design teams.Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings. Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.Preferred Qualifications
15+ years of experience in logic design delivering complex solutions.10+ years of experience in one or more of the following – floating point arithmetic and datapath design, Direct Memory Access(DMA) design, subsystem designs/integration, or custom logic design.5+ years of experience managing and leading logic design teams.Multiple successful Application specific Integrated Circuit(ASIC) tape outs in deep sub-micron technologies.Experience with scripting language such as Python or Perl.Experience debugging designs as well as simulation environment.Knowledge of verification principles, testbenches, Universal Verification Methodology(UVM), and coverage.Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs.Working knowledge of writing assertions, coverage and formal verification.Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
Microsoft Careers .Microsoft will accept applications for the role until May 27, 2024.Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
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