Advanced Micro Devices
Fellow Software Architect
Advanced Micro Devices, San Jose, California, United States, 95199
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
THE ROLE:
We are looking for a Fellow Software Architect to lead specification and development of FPGA Static Timing Analysis (STA) features for the next generation STA tools. You will provide technical leadership and architectural guidance to help advance STA capabilities on current and future devices, with focus on performance, accuracy, and quality.
THE PERSON:
If you are someone with great depth of experience in STA development who is ready to contribute immediately to improving current software features and performance. Passionate about work, self-motivated, detail oriented and able to work both independently and collaboratively in a dynamic, fast-paced environment. Someone that has insight into performance optimizations and will be able to think of novel solutions, implementing them from concept to production. If you possess the drive and passion and vision to build the software roadmap for the STA capabilities, this is the role for you!
KEY RESPONSIBILITIES:
Designing, implementing, and testing FPGA STA capabilities, suitable for placement, optimization, routing and signoff timing.
Conducting research and development of novel STA algorithms and optimization of existing STA algorithms to deliver multi-fold improvements in quality of results (QOR), runtime, and memory, while maintaining timing accuracy.
Evaluating and providing STA support for new FPGA architectures.
Working with the field on closing critical customer design issues.
Collaborating with Tech Marketing and Applications Engineering to understand customer needs and drive required STA support.
PREFERRED EXPERIENCE:
Extensive experience in architecting and implementing high performance, high-capacity STA engines.
Comprehensive understanding of multi-mode / multi corner and variation aware STA.
Experience working with multi-threaded / multi-process programs.
Expertise in state-of-the-art EDA algorithms.
Detailed knowledge of SDC timing constraints.
Knowledge of Digital Design and FPGA implementation.
Proficiency in C++ Programming.
Solid foundation in software engineering, with strong analytical and debugging skills.
Excellent verbal communication and writing skills and executive level presentation skills.
Experience with TCL, Python, Perl, or other scripting languages.
Comfortable with communicating with all levels of the organization especially executive level.
ACADEMIC CREDENTIALS:
Master's degree or PhD in Electrical Engineering or Computer Science or related equivalent.
LOCATION:
Longmont, CO, or San Jose, CA
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#LI-HYBRID
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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
THE ROLE:
We are looking for a Fellow Software Architect to lead specification and development of FPGA Static Timing Analysis (STA) features for the next generation STA tools. You will provide technical leadership and architectural guidance to help advance STA capabilities on current and future devices, with focus on performance, accuracy, and quality.
THE PERSON:
If you are someone with great depth of experience in STA development who is ready to contribute immediately to improving current software features and performance. Passionate about work, self-motivated, detail oriented and able to work both independently and collaboratively in a dynamic, fast-paced environment. Someone that has insight into performance optimizations and will be able to think of novel solutions, implementing them from concept to production. If you possess the drive and passion and vision to build the software roadmap for the STA capabilities, this is the role for you!
KEY RESPONSIBILITIES:
Designing, implementing, and testing FPGA STA capabilities, suitable for placement, optimization, routing and signoff timing.
Conducting research and development of novel STA algorithms and optimization of existing STA algorithms to deliver multi-fold improvements in quality of results (QOR), runtime, and memory, while maintaining timing accuracy.
Evaluating and providing STA support for new FPGA architectures.
Working with the field on closing critical customer design issues.
Collaborating with Tech Marketing and Applications Engineering to understand customer needs and drive required STA support.
PREFERRED EXPERIENCE:
Extensive experience in architecting and implementing high performance, high-capacity STA engines.
Comprehensive understanding of multi-mode / multi corner and variation aware STA.
Experience working with multi-threaded / multi-process programs.
Expertise in state-of-the-art EDA algorithms.
Detailed knowledge of SDC timing constraints.
Knowledge of Digital Design and FPGA implementation.
Proficiency in C++ Programming.
Solid foundation in software engineering, with strong analytical and debugging skills.
Excellent verbal communication and writing skills and executive level presentation skills.
Experience with TCL, Python, Perl, or other scripting languages.
Comfortable with communicating with all levels of the organization especially executive level.
ACADEMIC CREDENTIALS:
Master's degree or PhD in Electrical Engineering or Computer Science or related equivalent.
LOCATION:
Longmont, CO, or San Jose, CA
#LI-DW1
#LI-HYBRID
#J-18808-Ljbffr