NXP Semiconductors
Senior ASIC Design Engineer
NXP Semiconductors, San Jose, California, United States, 95199
Senior ASIC Design Engineer
ApplyLocations: San Jose (Holger Way)Time Type: Full TimePosted On: Posted 3 Days AgoJob Requisition ID: R-10056067Developing the best in class products with the latest IEEE standards in advanced processing nodes and lead the next generation of innovations including Wi-Fi 7 technologies. In connection with such duties, the Beneficiary will develop micro-architecture of complex DSP blocks; RTL coding, verification and documentation; area/power optimization and design tradeoff analysis; script development and design automation; logic synthesis and timing closure; demonstrate fluency in RTL coding in Verilog/System Verilog, in-depth knowledge on digital logic design, DSP, and communication, experience in UVM or other verification methodology; experience in WiFi or other communication standard.Qualifications:Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, foreign equivalent or closely related field.Two (2) years of progressive, post-baccalaureate experience in job offered or similar occupation (all levels accepted) such as Engineering Staff, Design Layout TL or closely related.Required Skills:Two (2) years of experience in:RTL Design using Verilog and System Verilog;Clock Domain Crossing;Block Level Testing;CAD Tools Questa/Modelsim, Cadence Spyglass, Cadence Virtuoso, Conformal, Synopsys PrimeTime(PT), Design Compiler;Scripting Languages like Python, Perl or TCL;Logic design simulators (e.g. VCS/Verdi, Simvision); andKnowledge of digital signal processing algorithms.Annual Salary: $160,000The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health, dental, and vision insurance, 401(k), and paid leave. Please note that the base salary range (or hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $125,600 to $172,700 annually.NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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ApplyLocations: San Jose (Holger Way)Time Type: Full TimePosted On: Posted 3 Days AgoJob Requisition ID: R-10056067Developing the best in class products with the latest IEEE standards in advanced processing nodes and lead the next generation of innovations including Wi-Fi 7 technologies. In connection with such duties, the Beneficiary will develop micro-architecture of complex DSP blocks; RTL coding, verification and documentation; area/power optimization and design tradeoff analysis; script development and design automation; logic synthesis and timing closure; demonstrate fluency in RTL coding in Verilog/System Verilog, in-depth knowledge on digital logic design, DSP, and communication, experience in UVM or other verification methodology; experience in WiFi or other communication standard.Qualifications:Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, foreign equivalent or closely related field.Two (2) years of progressive, post-baccalaureate experience in job offered or similar occupation (all levels accepted) such as Engineering Staff, Design Layout TL or closely related.Required Skills:Two (2) years of experience in:RTL Design using Verilog and System Verilog;Clock Domain Crossing;Block Level Testing;CAD Tools Questa/Modelsim, Cadence Spyglass, Cadence Virtuoso, Conformal, Synopsys PrimeTime(PT), Design Compiler;Scripting Languages like Python, Perl or TCL;Logic design simulators (e.g. VCS/Verdi, Simvision); andKnowledge of digital signal processing algorithms.Annual Salary: $160,000The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health, dental, and vision insurance, 401(k), and paid leave. Please note that the base salary range (or hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $125,600 to $172,700 annually.NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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