Infinera Corporation
Mixed-Signal Design Engineer
Infinera Corporation, San Jose, California, United States, 95199
Mixed-Signal Design EngineerApply
Locations: CA, San Jose - Office
Time Type: Full time
Posted on: Posted 2 Days Ago
Job Requisition ID: 2023648
CA Pay Range (Annual):
At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.
Infinera also offers paid leave, medical, dental, and vision coverage, 401(k), life, and disability insurance to eligible employees.
Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop, and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine networks.
The successful candidate shall lead the design efforts of high-speed low-noise clocking circuitry, including the fractional-N phase locked loops and the clock distribution networks.
The high-quality clocking circuitry is the backbone of the high-speed mixed-signal IPs under development here at Infinera. You will have the great chance to demonstrate your creativity and superior technical competency by leading the design efforts to help Infinera hold the market leadership. We together will revolutionize the era of efficient high-speed transmission.
Essential Functions and Key Responsibilities:
Design, simulate, and verify the high frequency fractional-N PLLs.
Architect, model, and simulate the noise accumulation and the skew of the clock distribution trees.
Model, optimize, and measure the phase noise and jitter performance, and the skew of the whole clocking networks.
Design and implement the high-frequency / low-noise VCOs.
Collaborate and/or supervise other team members for system design implementation, layout floor planning, and system level modeling.
Mandatory Knowledge/Skills/Abilities:
Have exposure in designing low phase noise LC-VCO based PLLs to production.
Abundant knowledge in the design trade-offs among different VCO topologies for MM-Wave applications, including but not limited to LC-VCO, TWO, SWO, etc.
Hands-on in designing the clock distribution network in Cadence environment.
Good at modeling the phase noise and spurs of the frac-N PLLs.
Possess extensive experience in designing and implementing high frequency VCOs and clock trees with EMX tools.
Have a decent understanding in CMOS analog/mixed signal design overall.
Preferred Knowledge/Skill/Abilities:
Good at supervising testing activities.
Fluent in verbal and written communications.
Independently resolves issues and conquers design challenges.
Self-motivated and detail-oriented.
Has good interpersonal skills.
Education Requirements:
M.S. or Ph.D. in E.E.
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law.
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Locations: CA, San Jose - Office
Time Type: Full time
Posted on: Posted 2 Days Ago
Job Requisition ID: 2023648
CA Pay Range (Annual):
At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.
Infinera also offers paid leave, medical, dental, and vision coverage, 401(k), life, and disability insurance to eligible employees.
Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop, and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine networks.
The successful candidate shall lead the design efforts of high-speed low-noise clocking circuitry, including the fractional-N phase locked loops and the clock distribution networks.
The high-quality clocking circuitry is the backbone of the high-speed mixed-signal IPs under development here at Infinera. You will have the great chance to demonstrate your creativity and superior technical competency by leading the design efforts to help Infinera hold the market leadership. We together will revolutionize the era of efficient high-speed transmission.
Essential Functions and Key Responsibilities:
Design, simulate, and verify the high frequency fractional-N PLLs.
Architect, model, and simulate the noise accumulation and the skew of the clock distribution trees.
Model, optimize, and measure the phase noise and jitter performance, and the skew of the whole clocking networks.
Design and implement the high-frequency / low-noise VCOs.
Collaborate and/or supervise other team members for system design implementation, layout floor planning, and system level modeling.
Mandatory Knowledge/Skills/Abilities:
Have exposure in designing low phase noise LC-VCO based PLLs to production.
Abundant knowledge in the design trade-offs among different VCO topologies for MM-Wave applications, including but not limited to LC-VCO, TWO, SWO, etc.
Hands-on in designing the clock distribution network in Cadence environment.
Good at modeling the phase noise and spurs of the frac-N PLLs.
Possess extensive experience in designing and implementing high frequency VCOs and clock trees with EMX tools.
Have a decent understanding in CMOS analog/mixed signal design overall.
Preferred Knowledge/Skill/Abilities:
Good at supervising testing activities.
Fluent in verbal and written communications.
Independently resolves issues and conquers design challenges.
Self-motivated and detail-oriented.
Has good interpersonal skills.
Education Requirements:
M.S. or Ph.D. in E.E.
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law.
#J-18808-Ljbffr