Cadence Design Systems
Principal Design Engineer
Cadence Design Systems, San Jose, California, United States, 95199
Profile insightsFind out how your skills align with the job description.
SkillsDo you have experience in
SoC ?
EducationDo you have a
Master's degree ?
Job detailsHere’s how the job details align with your profile.
Pay$131,600 - $244,400 a year
Job typeFull-time
LocationSan Jose, CA
Benefits
401(k) matching
Employee stock purchase plan
Health insurance
Paid holidays
Vision insurance
Full job descriptionAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL integration, maintaining the timing constraint, synthesis, place and route, static timing analysis (STA), timing closure, power optimization, and physical verification for both block and chip top level.
You will also be responsible for interfacing with the Physical Design team on STA, timing closure, and P&R, and participating in silicon bring up with the validation team.
Job Requirements
BSEE and at least 3-5 years of prior experience required. MSEE and at least 1-3 years of prior experience strongly preferred.
Prior experience in timing and/or RTL design of high-speed interfaces.
Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
Knowledge of the IP/SoC level timing closure flow and methodology.
Strong command of synthesis, STA, design for test, and design methodologies.
Ability to handle multiple projects/tasks successfully.
Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow.
Hands-on experience in timing constraints generation and management.
Proficiency in scripting languages (TCL and Perl).
Proficiency with synthesis, logic equivalence, DFT, and backend related methodology and tools.
Strong background in constraint analysis and debug, using industry standard tools.
Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at-speed, and BIST testing.
Team player with a passion to innovate and a can-do attitude.
Self-starter and highly motivated.
Desired Skills
Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs.
The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
#J-18808-Ljbffr
SkillsDo you have experience in
SoC ?
EducationDo you have a
Master's degree ?
Job detailsHere’s how the job details align with your profile.
Pay$131,600 - $244,400 a year
Job typeFull-time
LocationSan Jose, CA
Benefits
401(k) matching
Employee stock purchase plan
Health insurance
Paid holidays
Vision insurance
Full job descriptionAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL integration, maintaining the timing constraint, synthesis, place and route, static timing analysis (STA), timing closure, power optimization, and physical verification for both block and chip top level.
You will also be responsible for interfacing with the Physical Design team on STA, timing closure, and P&R, and participating in silicon bring up with the validation team.
Job Requirements
BSEE and at least 3-5 years of prior experience required. MSEE and at least 1-3 years of prior experience strongly preferred.
Prior experience in timing and/or RTL design of high-speed interfaces.
Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
Knowledge of the IP/SoC level timing closure flow and methodology.
Strong command of synthesis, STA, design for test, and design methodologies.
Ability to handle multiple projects/tasks successfully.
Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow.
Hands-on experience in timing constraints generation and management.
Proficiency in scripting languages (TCL and Perl).
Proficiency with synthesis, logic equivalence, DFT, and backend related methodology and tools.
Strong background in constraint analysis and debug, using industry standard tools.
Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at-speed, and BIST testing.
Team player with a passion to innovate and a can-do attitude.
Self-starter and highly motivated.
Desired Skills
Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs.
The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
#J-18808-Ljbffr