Synopsys, Inc.
ASIC Digital Design, Staff Engineer
Synopsys, Inc., Sunnyvale, California, United States, 94087
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, the cloud, 5G, and the Internet of Things are ushering in the Era of Smart Everything. We’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
ASIC Digital Design, Staff EngineerDDR IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR IP products. All current and next-generation technologies are being developed by the DDR IP team, with both digital and analog components complementing each other to create a high-performance, high-bandwidth, low-latency, and low-power product.
We are looking for a Senior ASIC Digital Design Engineer to join Synopsys Solution Group, DDRPHY IP team to innovate and develop the latest world-class market-leading DesignWare DDRPHY IP solution.
Responsibilities
Digital microarchitecture definition and documentationRTL logic design, debug, and verification for best timing, area, and powerRequired Skills
BS/MS in Electronics Engineering with at least 5 years of design experienceExperience with synthesizable Verilog and System Verilog design concepts and implementationExperience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniquesExhibit excellent communication skills and be self-motivatedUnderstanding of DDR memory and DDRPHY architecture is a plus
The base salary range across the U.S. for this role is between $122,000-$182,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.#J-18808-Ljbffr
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, the cloud, 5G, and the Internet of Things are ushering in the Era of Smart Everything. We’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
ASIC Digital Design, Staff EngineerDDR IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR IP products. All current and next-generation technologies are being developed by the DDR IP team, with both digital and analog components complementing each other to create a high-performance, high-bandwidth, low-latency, and low-power product.
We are looking for a Senior ASIC Digital Design Engineer to join Synopsys Solution Group, DDRPHY IP team to innovate and develop the latest world-class market-leading DesignWare DDRPHY IP solution.
Responsibilities
Digital microarchitecture definition and documentationRTL logic design, debug, and verification for best timing, area, and powerRequired Skills
BS/MS in Electronics Engineering with at least 5 years of design experienceExperience with synthesizable Verilog and System Verilog design concepts and implementationExperience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniquesExhibit excellent communication skills and be self-motivatedUnderstanding of DDR memory and DDRPHY architecture is a plus
The base salary range across the U.S. for this role is between $122,000-$182,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.#J-18808-Ljbffr