Astera Labs
Product/Test Engineer (Internship 2025)
Astera Labs, Santa Clara, California, us, 95053
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at
www.asteralabs.com
Job Description
We are looking for exceptional engineering candidates excited about opportunities in Test Engineering, Product Engineering, and manufacturing engineering roles. The ideal candidate will support yield enhancement, SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp.
Basic Qualifications
Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred.Coursework related to semiconductor manufacturing, testing, yield, or related areasProfessional attitude with ability to execute on multiple tasks with minimal supervision.Strong team player with good communication skills to work alongside a team of high caliber engineers.Entrepreneurial, open-mind behavior and can-do attitude.Preferred Experience
Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.Collaboration with design team to define test strategy, create and own test plan.Tester platform selection, design, and development of ATE hardware for wafer sort and final test.Familiar with high-speed load board design techniques.Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage - SCAN, MEMBIST, SerDes and other functional tests.Skilled in control interfaces - I2C, I3C, SPI, MDIO, JTAG etc.Expertise in production test of high speed SerDes operating at 16Gbps and higher.Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.Experience with lab equipment including protocol analyzers and oscilloscopes.Experience with using Advantest 93k ATE platform.Proficiency in, at least, one modern programming language such as C/C++, Python.
The base hourly pay for this role is $35-45. Your base pay will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
www.asteralabs.com
Job Description
We are looking for exceptional engineering candidates excited about opportunities in Test Engineering, Product Engineering, and manufacturing engineering roles. The ideal candidate will support yield enhancement, SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp.
Basic Qualifications
Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred.Coursework related to semiconductor manufacturing, testing, yield, or related areasProfessional attitude with ability to execute on multiple tasks with minimal supervision.Strong team player with good communication skills to work alongside a team of high caliber engineers.Entrepreneurial, open-mind behavior and can-do attitude.Preferred Experience
Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.Collaboration with design team to define test strategy, create and own test plan.Tester platform selection, design, and development of ATE hardware for wafer sort and final test.Familiar with high-speed load board design techniques.Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage - SCAN, MEMBIST, SerDes and other functional tests.Skilled in control interfaces - I2C, I3C, SPI, MDIO, JTAG etc.Expertise in production test of high speed SerDes operating at 16Gbps and higher.Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.Experience with lab equipment including protocol analyzers and oscilloscopes.Experience with using Advantest 93k ATE platform.Proficiency in, at least, one modern programming language such as C/C++, Python.
The base hourly pay for this role is $35-45. Your base pay will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.