Chelsea Search Group, Inc.
Semiconductor Test Engineer (Advantest V93000)
Chelsea Search Group, Inc., San Jose, California, United States, 95199
Semiconductor Test Engineer (Advantest V93000)
San Jose, California (onsite)
US Citizen or US Permanent Resident
12+ months contract with possible extensions
Role/ Responsibilities:
Test Engineer responsible for developing test program and design of hardware on ATE (Automated Testing Equipment) for product bring up, characterization and eventual mass production testing of very high-performance SOC semiconductor devices.
Develop test plans and support various phases of manufacturing including product bring up, reliability testing, characterization, production releases and failure analysis.
Should be fully capable in optimally utilizing all ATE resources for providing a low cost of test (CoT) without compromising on outgoing product quality.
Work closely with the design engineers on the first silicon debug, device characterization, test program bring up and production release activities.
Involve on test program hand off, production release, yield improvement and test time reduction.
High level of collaboration and interaction with different Product Engineering, Design Engineering, Quality Engineering, and Foundry Engineering teams.
Responsible for all phases of product test development and should plan/track schedule to reduce time to market.
Skill in programming language C, C++, Java, shell script languages like PERL and Python.
Experience with ATE platforms such as V93000 is required.
Background in Digital, Mixed-Signal testing is highly desirable.
Skills Required:
3+ years of Semiconductor Test Engineering experience.
Hands on experience with Advantest V93000, SMT8 version is added advantage.
Solid understanding of Semiconductor Design for Test (DFT) techniques and Debug of digital vectors (JTAG/SCAN/ATPG / Functional / Memory BIST).
Mixed-Signal test engineering experience is added advantage.
Experience/knowledge in new product development, characterization, qualification and strong analytical skills, ability to problem solve and debug systems, circuits, and devices.
Experienced in product coordination, yield improvement & test time reduction.
Hands-on experience with production & characterization data collection at wafer as well as package level.
Strong analytical and problem-solving ability with desire to perform hands-on work within a lab environment is a must.
Excellent communication skills as well as detail-oriented work ethic and project management knowledge.
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San Jose, California (onsite)
US Citizen or US Permanent Resident
12+ months contract with possible extensions
Role/ Responsibilities:
Test Engineer responsible for developing test program and design of hardware on ATE (Automated Testing Equipment) for product bring up, characterization and eventual mass production testing of very high-performance SOC semiconductor devices.
Develop test plans and support various phases of manufacturing including product bring up, reliability testing, characterization, production releases and failure analysis.
Should be fully capable in optimally utilizing all ATE resources for providing a low cost of test (CoT) without compromising on outgoing product quality.
Work closely with the design engineers on the first silicon debug, device characterization, test program bring up and production release activities.
Involve on test program hand off, production release, yield improvement and test time reduction.
High level of collaboration and interaction with different Product Engineering, Design Engineering, Quality Engineering, and Foundry Engineering teams.
Responsible for all phases of product test development and should plan/track schedule to reduce time to market.
Skill in programming language C, C++, Java, shell script languages like PERL and Python.
Experience with ATE platforms such as V93000 is required.
Background in Digital, Mixed-Signal testing is highly desirable.
Skills Required:
3+ years of Semiconductor Test Engineering experience.
Hands on experience with Advantest V93000, SMT8 version is added advantage.
Solid understanding of Semiconductor Design for Test (DFT) techniques and Debug of digital vectors (JTAG/SCAN/ATPG / Functional / Memory BIST).
Mixed-Signal test engineering experience is added advantage.
Experience/knowledge in new product development, characterization, qualification and strong analytical skills, ability to problem solve and debug systems, circuits, and devices.
Experienced in product coordination, yield improvement & test time reduction.
Hands-on experience with production & characterization data collection at wafer as well as package level.
Strong analytical and problem-solving ability with desire to perform hands-on work within a lab environment is a must.
Excellent communication skills as well as detail-oriented work ethic and project management knowledge.
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