Logo
Jobot

FPGA Design Engineer

Jobot, Los Angeles, CA, United States


Calling all FPGA Design Engineers

This Jobot Job is hosted by: Mordy Ornguze

Are you a fit? Easy Apply now by clicking the "Apply Now" button
and sending us your resume.

Salary: $113,000 - $170,000 per year

A bit about us:

We're a telecommunications infrastructure leader that powered the deployments of 3G and 4G. Today we're developing the 5G Fronthaul solution that will enable fully featured 5G networks to lead the next generation of connectivity for people and machines. We provide our customers with network connectivity solutions that allow them to change the world.

Why join us?

Benefits include:

  • Competitive salary
  • Paid Time off
  • Medical, Dental and Vision Insurance
Job Details

About the Role:

We are looking for a dynamic FPGA engineering professional to join our Product Development team, and work on cutting edge 5G Fronthaul and Backhaul Ethernet transport products. This position requires a person who can demonstrate expertise in, high speed digital design, can operate under minimal supervision, is a self-motivated fast learner, and is highly competent in developing innovative hardware solutions for the emerging 5G markets

What you'll do:

High speed LAN/WAN system/FPGA design and verification for FPGA based network applications.

What we're looking for:

  • Knowledge of high speed digital design principals
  • Experience with Verilog/VHDL for Xilinx/Altera devices and their compilation/simulation software suites
  • Experienced in using FPGA and Software development tools.
  • Experience with Static Timing Analysis
  • Good communication skills (written and verbal)
  • Track record of taking successful and reliable designs from concept to production
  • 25G or 100G product development a plus.
  • Strong troubleshooting skills and familiarity with test instruments
  • Experience with scripting languages Tcl, Python, PERL
  • Software experience with C / C++
  • Knowledge of PCI, I2C, SPI, and various CPUs, DSPs, PHYs

Must Have:

The successful candidate will have experience in or knowledge of:

  • Bachelor’s degree in Electrical Engineering.
  • 5 -7 years’ experience in Verilog/VHDL for Xilinx/Altera devices and their compilation/simulation software suites.
  • Strong troubleshooting skills and familiarity with test instruments.
  • Proficient with a programming language like C/C++.

Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.