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Duties: Position: Senior Analog Design Verification Engineer Location: Dallas TX (Day-1 Onsite) What We Are Looking For: Understand the analog blocks at a high level – enough to understand how to control (V-AMS Verilog Analog Mixed Signal Blocks) learn/understand the testbench architecture understand how the DIGTOP block works at a high level – enough to know how to control/stimulate it create test sequences from high level description (this will likely require interaction to begin with) there are 3 types of tests: functional parametric dft/reliability create monitors to check the part is working as expected simulation over corners and check/report results review waveforms in simvision and create svcf files for sharing report status weekly What's In It for You: At-least 8+ years of experience in V-AMS At-least 5+ year of experience in SV/UVM. Device to test will be in LBC10 and include a large DIGTOP block (includes Arm M0 processor) and Analog front end (include type c detection logic, power paths that include OVP/UVP/Current limits, etc). Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM, C++ testbench Skills: Position: Senior Analog Design Verification Engineer Location: Dallas TX (Day-1 Onsite) What We Are Looking For: Understand the analog blocks at a high level – enough to understand how to control (V-AMS Verilog Analog Mixed Signal Blocks) learn/understand the testbench architecture understand how the DIGTOP block works at a high level – enough to know how to control/stimulate it create test sequences from high level description (this will likely require interaction to begin with)