Tenstorrent Inc
Architecture Staff Engineer, RTL Design, Chiplet Santa Clara, California, United
Tenstorrent Inc, Raleigh, North Carolina, United States,
Experienced engineer focused on Microarchitecture and RTL. The person coming into this role will work on the implementation of digital IPs for Tenstorrent’s CPU and AI/ML accelerator chiplets.
This role is Hybrid, based out of Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
RTL design and Microarchitecture of a system management, security sub-systems, fabric, and SoC integration.
RTL coding in Verilog leveraging both industry tools as well as open-source infrastructure.
Work with design, test, and post-silicon validation teams for high-quality delivery of the security subsystem.
Evaluate and integrate 3rd party IP components in the design.
Drive trade-offs for your logic by working closely with architecture, DV, and physical design engineers to craft optimal solutions that meet the design goals.
Deploy innovative techniques for improving power, performance, and area of the design, drive experiments with RTL, and evaluate synthesis, timing, and power results.
Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environments.
Enhance RTL design environment, tools, and infrastructure.
Experience & Qualifications:
BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience.
Knowledge of industry standard protocols such as AXI, AHB, APB.
Expertise in logic design and ability to evaluate functional, performance, timing, and power for your design.
Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), synthesis, and power tools.
Expertise in microarchitecture definition and specification development.
Strong problem-solving and debug skills across various levels of design hierarchies.
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This role is Hybrid, based out of Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
RTL design and Microarchitecture of a system management, security sub-systems, fabric, and SoC integration.
RTL coding in Verilog leveraging both industry tools as well as open-source infrastructure.
Work with design, test, and post-silicon validation teams for high-quality delivery of the security subsystem.
Evaluate and integrate 3rd party IP components in the design.
Drive trade-offs for your logic by working closely with architecture, DV, and physical design engineers to craft optimal solutions that meet the design goals.
Deploy innovative techniques for improving power, performance, and area of the design, drive experiments with RTL, and evaluate synthesis, timing, and power results.
Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environments.
Enhance RTL design environment, tools, and infrastructure.
Experience & Qualifications:
BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience.
Knowledge of industry standard protocols such as AXI, AHB, APB.
Expertise in logic design and ability to evaluate functional, performance, timing, and power for your design.
Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), synthesis, and power tools.
Expertise in microarchitecture definition and specification development.
Strong problem-solving and debug skills across various levels of design hierarchies.
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