Alif Semiconductor
Sr. Digital Implementation Engineer
Alif Semiconductor, Irvine, California, United States, 92713
Alif Semiconductor is revolutionizing the way secure connected AI-enabled embedded solutions are created. We are looking for motivated individuals who want to be involved in a fast-paced environment with cutting-edge technology.You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT devices. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology. This position requires expert knowledge of ASIC synthesis flow (including STA/DFT and IP integration).
Additional Responsibilities
Run complete synthesis flowDefine and document synthesis (including DFT insertion) methodology and scripts/flowsUPF flow for defining power intent (at block and chip level)RTL and Netlist hand-off checks (LEC)Interface with Physical Design for floor-planning and timing closureAssist with design partitioning and floorplanAnalyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teamsRequired Qualifications
Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing ClosureFamiliarity with DFT (Tessent) and back-end (Cadence) toolsHands-on experience with digital logic synthesis for power and area optimizationExperience in low power design issues, tools, and methodology including UPF power intent specificationProficient in Verilog/SV/Tcl/Perl/PythonHighly motivated to debug and resolve CAD tool flow issuesSelf-starter with good analytical, problem solving and communication skillsBachelor’s degree in Electrical Engineering, a related discipline, or equivalent experiencePreferred Qualifications
Strong expertise with Design Compiler or GenusExperience with IP integrationExperience with Synthesis, LEC, DFT, BISTExperience with Cadence Timing and ECO FlowExperience with Clock Domain Crossing (CDC) AnalysisExperience with timing corner selection and library modelsProven track record of successful deep submicron technology node tapeout (including Silicon bring-up)Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT)
Alif Semiconductor provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.
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Additional Responsibilities
Run complete synthesis flowDefine and document synthesis (including DFT insertion) methodology and scripts/flowsUPF flow for defining power intent (at block and chip level)RTL and Netlist hand-off checks (LEC)Interface with Physical Design for floor-planning and timing closureAssist with design partitioning and floorplanAnalyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teamsRequired Qualifications
Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing ClosureFamiliarity with DFT (Tessent) and back-end (Cadence) toolsHands-on experience with digital logic synthesis for power and area optimizationExperience in low power design issues, tools, and methodology including UPF power intent specificationProficient in Verilog/SV/Tcl/Perl/PythonHighly motivated to debug and resolve CAD tool flow issuesSelf-starter with good analytical, problem solving and communication skillsBachelor’s degree in Electrical Engineering, a related discipline, or equivalent experiencePreferred Qualifications
Strong expertise with Design Compiler or GenusExperience with IP integrationExperience with Synthesis, LEC, DFT, BISTExperience with Cadence Timing and ECO FlowExperience with Clock Domain Crossing (CDC) AnalysisExperience with timing corner selection and library modelsProven track record of successful deep submicron technology node tapeout (including Silicon bring-up)Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT)
Alif Semiconductor provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.
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