R&D Sr. Staff Design Engineer – DDR/HBM PHY Architecture

R&D Sr. Staff Design Engineer – DDR/HBM PHY ArchitectureWe’re looking for a PHY architect to join the DDR/HBM PHY architecture team.In this position, you will be part of an architecture team that plans and executes the design for the next-generation DDR and HBM PHYs in the Synopsys IP portfolio. The job entails working with senior architects to understand standard specifications, evaluate ideas, draft specifications, and enable a larger team of design engineers bringing new ideas into silicon. You’d leverage your understanding of computer architecture, mixed-signal design, off-chip signaling, RTL development, design-for-test, and logical verification to create leading-edge products. Supporting Synopsys’ customers is also an important part of the role. You will join a collaborative, multi-person engineering team engaged in similar activities on related DDR and HBM PHY development projects.Job Responsibilities:With the guidance of a senior architect, understand marketing, customer desires and standard specification and translate those into a set of product design features and functions of ongoing and future designs to create best-in-class products.Generate the functional description for the product, creating specifications describing the interface components, operation, structure, and behavioral parameters.Develop models representing the performance features of interface design sub-components.Solve design execution problems tied to the product definition.Perform feasibility studies through the evaluation of trial designs.Document results, conclusions, and technical insights into performance, power, area, and functional parameters.Interact and communicate with design teams performing digital design and verification, analog circuit design and verification, and layout design.Support customers in their implementation of the product.Key Qualifications and Experience:Possesses a minimum of 8+ years of related experience or an advanced degree with 6+ years of related experience.Understands high-speed interface principles, such as mixed-signal design and off-chip signaling.Skilled in generating and supporting documentation through written specifications, and communicating those specifications within a design team and to external customers.Well-versed in RTL logic design, simulation, test planning, and verification of complex integrated circuit components.Knowledgeable in design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints.Able to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge design.Skilled in troubleshooting and debugging of mixed-signal interfaces.Knowledge in DDR protocols and JEDEC spec is a plus.Experience with GenAI in the design process is a plus.Able to work autonomously with high-level guidance.The Salary Range for this position is $142,000 - $213,000.

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