NVIDIA
Senior DFT Methodology Engineer
NVIDIA, Santa Clara, California, us, 95053
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.DFX Methodology Group at NVIDIA works on groundbreaking innovations involving crafting creative solutions for cutting edge test techniques, in-system test architecture, as well as verification and post-silicon validation on some of the industry's most complex semiconductor chips.What you'll be doing:As a member in our team, you will work next generation test architectures. You will work with multi-functional teams, implementing brand-new designs in test access mechanisms, high-speed test interfaces, and in-system test architecture.
In addition, you will help develop and deploy In-System Test (IST) methodologies for our next generation products for scan architecture, ATPG, MBIST, and IOBIST applications.
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:BSEE (or equivalent experience) with 5+, MSEE with 3+, or PhD with 2+ years of experience in DFT, system architecture, or RTL design.
Understanding of fundamental DFT topics, such as, fault modeling, ATPG and fault simulation. Tessent ATPG/SSN experience is a plus.
Excellent understanding of MBIST and IOBIST fundamentals.
Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe protocol.
Knowledge of high-speed interface architectures such as PCIe, USB3, DDR is a plus.
Excellent analytical skills in verification and validation of logic on complex and multi-million gate designs using vendor tools.
Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.
Experience in Silicon debug and bring-up on the ATE or SLT platforms.
Strong programming and scripting skills in Perl, Python or Tcl desired.
Outstanding written and oral communication skills with the curiosity to work on rare challenges.
NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you!#LI-HybridThe base salary range is 128,000 USD - 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and
benefits .
NVIDIA accepts applications on an ongoing basis.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.#J-18808-Ljbffr
In addition, you will help develop and deploy In-System Test (IST) methodologies for our next generation products for scan architecture, ATPG, MBIST, and IOBIST applications.
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:BSEE (or equivalent experience) with 5+, MSEE with 3+, or PhD with 2+ years of experience in DFT, system architecture, or RTL design.
Understanding of fundamental DFT topics, such as, fault modeling, ATPG and fault simulation. Tessent ATPG/SSN experience is a plus.
Excellent understanding of MBIST and IOBIST fundamentals.
Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe protocol.
Knowledge of high-speed interface architectures such as PCIe, USB3, DDR is a plus.
Excellent analytical skills in verification and validation of logic on complex and multi-million gate designs using vendor tools.
Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.
Experience in Silicon debug and bring-up on the ATE or SLT platforms.
Strong programming and scripting skills in Perl, Python or Tcl desired.
Outstanding written and oral communication skills with the curiosity to work on rare challenges.
NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you!#LI-HybridThe base salary range is 128,000 USD - 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and
benefits .
NVIDIA accepts applications on an ongoing basis.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.#J-18808-Ljbffr