Tenstorrent Inc
CPU Core Feature Verification and Debug Engineer
Tenstorrent Inc, Austin, Texas, us, 78716
We are looking for a CPU core level feature / testplan verification engineer responsible for ISA and microarchitectural verification.
Responsibilities:
Functional verification with emphasis on core level testplanning, stimulus development and regression debug for simulation and emulation regressions
Understand ISA and microarchitectural specifications for the Core and create comprehensive testplans
Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
Develop architectural and microarchitectural coverage for core features and create stimulus for closing coverage in a timely manner
Support design deployment across simulation and emulation platforms
Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster
Experience & Qualifications:
BS/MS/PhD in EE/ECE/CE/CS with at least 3 years of experience
Strong background and experience with high performance OOO CPU microarchitecture
Experience and understanding of one or more ISAs - x86, ARM or RISCV
Experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
Familiar with simulation, formal and emulation environments
Hands-on with scripting (Python, PERL)
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies
Location
Multiple geographies: Austin, Santa Clara, Bangalore
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.
As this position will have direct and/or indirect access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency informationand/or documentation will be required and considered as Tenstorrent moves through the employment process.
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Responsibilities:
Functional verification with emphasis on core level testplanning, stimulus development and regression debug for simulation and emulation regressions
Understand ISA and microarchitectural specifications for the Core and create comprehensive testplans
Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
Develop architectural and microarchitectural coverage for core features and create stimulus for closing coverage in a timely manner
Support design deployment across simulation and emulation platforms
Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster
Experience & Qualifications:
BS/MS/PhD in EE/ECE/CE/CS with at least 3 years of experience
Strong background and experience with high performance OOO CPU microarchitecture
Experience and understanding of one or more ISAs - x86, ARM or RISCV
Experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
Familiar with simulation, formal and emulation environments
Hands-on with scripting (Python, PERL)
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies
Location
Multiple geographies: Austin, Santa Clara, Bangalore
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.
As this position will have direct and/or indirect access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency informationand/or documentation will be required and considered as Tenstorrent moves through the employment process.
#J-18808-Ljbffr