ideaVat
ASIC Engineer
ideaVat, San Jose, California, United States, 95199
Ideavat provides I.T staffing solutions, enabling companies & jobseekers engage successfully.
With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers/hiring managers, helping them identify key talents. Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data/Hadoop developers & architects…& more) remains our primary focus!
Job Description
Job Title: ASIC EngineerLocation: San Jose, CADuration: 6 Months
Minimum Required Skills:ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation, Synthesis / Conformal (Cadence Tool for formal verification)
Description:Should have 2-5 years of experience in FPGA/ASIC DevelopmentBuild RTL designs of digital circuits using VHDL and System VerilogPerform frontend design development and integration of large ASIC designsCollaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.Write design documents including high level interface descriptions and design descriptions.Write function test cases and test benches to verify functionality of designsTeam work and proactive sharing of knowledgeComfortable working in a fast paced environment.Qualifications
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation, Synthesis / Conformal (Cadence Tool for formal verification)
Additional Information
All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr
With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers/hiring managers, helping them identify key talents. Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data/Hadoop developers & architects…& more) remains our primary focus!
Job Description
Job Title: ASIC EngineerLocation: San Jose, CADuration: 6 Months
Minimum Required Skills:ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation, Synthesis / Conformal (Cadence Tool for formal verification)
Description:Should have 2-5 years of experience in FPGA/ASIC DevelopmentBuild RTL designs of digital circuits using VHDL and System VerilogPerform frontend design development and integration of large ASIC designsCollaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.Write design documents including high level interface descriptions and design descriptions.Write function test cases and test benches to verify functionality of designsTeam work and proactive sharing of knowledgeComfortable working in a fast paced environment.Qualifications
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation, Synthesis / Conformal (Cadence Tool for formal verification)
Additional Information
All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr