Mars
Packaging Signal Integrity/Power Integrity Engineer
Mars, Sunnyvale, California, United States, 94087
Minimum qualifications:
8 years of experience in chip package SI/PI design for interconnections (e.g., chip, package, and PCB level for high speed and high power products such as GPUs/ASIC/Chipsets).Experience in post silicon bring up or model correlation.Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D stacking, etc.).Preferred qualifications:
Experience with Redhawk on-chip analysis.Experience in programming and data analysis with MATLAB, Python, and C++ to establish automation flows.Understanding of VRM and system level power architecture.Familiarity with next generation memory, chiplet standards and timing budget methodology, including SI/PI co-analysis/design and channel design optimization.Signal and power integrity expertise for various IP blocks (e.g., high speed SerDes, PCIe, DDR3/4, LPDDR4/5, etc.).About the job
Our computational challenges are so big, complex, and unique we can't just purchase off-the-shelf hardware; we've got to make it ourselves. Your team designs and builds the hardware, software, and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.As a Signal Integrity/Power Integrity Engineer you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package, and system level. Within a concurrent engineering environment, you will be the main part of a larger team with system architects, ASIC engineers, and other SI/PI engineers.You will work with various cross-functional teams including the Chip Design team, Board Design team, System Design team, and vendors. You'll drive chip packaging signal and power implementations to meet chip, package, and system electrical requirements.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $146,000-$220,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.Responsibilities
Be responsible for chip package SI/PI analysis and creation of design recommendations for chip and systems from feasibility study to production.Develop SI/PI models for chip, packages interconnects, and complete SI/PI analysis of end-end design for serial and parallel interfaces for tape out.Develop topology, termination schemes, and rules for routing based on chip, package SI/PI analysis taking into account jitter, SSO, power distribution, core noise, cross-talk, and EMI/EMC.Drive chip-package-system co-design efforts to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc.Perform power integrity analysis for each PWR/GND domain: chip/package extraction, simulation, and decoupling strategy.
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8 years of experience in chip package SI/PI design for interconnections (e.g., chip, package, and PCB level for high speed and high power products such as GPUs/ASIC/Chipsets).Experience in post silicon bring up or model correlation.Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D stacking, etc.).Preferred qualifications:
Experience with Redhawk on-chip analysis.Experience in programming and data analysis with MATLAB, Python, and C++ to establish automation flows.Understanding of VRM and system level power architecture.Familiarity with next generation memory, chiplet standards and timing budget methodology, including SI/PI co-analysis/design and channel design optimization.Signal and power integrity expertise for various IP blocks (e.g., high speed SerDes, PCIe, DDR3/4, LPDDR4/5, etc.).About the job
Our computational challenges are so big, complex, and unique we can't just purchase off-the-shelf hardware; we've got to make it ourselves. Your team designs and builds the hardware, software, and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.As a Signal Integrity/Power Integrity Engineer you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package, and system level. Within a concurrent engineering environment, you will be the main part of a larger team with system architects, ASIC engineers, and other SI/PI engineers.You will work with various cross-functional teams including the Chip Design team, Board Design team, System Design team, and vendors. You'll drive chip packaging signal and power implementations to meet chip, package, and system electrical requirements.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $146,000-$220,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.Responsibilities
Be responsible for chip package SI/PI analysis and creation of design recommendations for chip and systems from feasibility study to production.Develop SI/PI models for chip, packages interconnects, and complete SI/PI analysis of end-end design for serial and parallel interfaces for tape out.Develop topology, termination schemes, and rules for routing based on chip, package SI/PI analysis taking into account jitter, SSO, power distribution, core noise, cross-talk, and EMI/EMC.Drive chip-package-system co-design efforts to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc.Perform power integrity analysis for each PWR/GND domain: chip/package extraction, simulation, and decoupling strategy.
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