Principal Digital Verification Engineer

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world --- come join our team and see how YOU can make a difference.A Principal Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.Essential Functions:UVM and System Verilog based Digital Verification environment definition and development.VIPs standardization, definition, development and documentation.Define VIP’s integration into the Project’s Digital Verification environment.Digital Verification Metrics definition for RTL and Gate-Level Verification.Test Plan definition and development.Digital Verification Automation and Scripting.Regression’s infrastructure definition, development and management.Close interaction with Senior Digital and Analog Designers to develop VIP models.Lead the Digital Verification Team.Lead and Supervise Digital Verification Tasks of multiple projects.Review Digital Verification Metrics and Results of multiple projects.Define and design Digital Verification Top-Level Tests.Analyze and debug test results, code coverage and functional coverage.Digital Verification estimation, planning and scheduling to meet tape-out dates.Qualifications:PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.10+ years of strong experience in ASIC Verification.Experience in power management DC-DC convertors + control topologies, such as PWM control, constant–on–time control, and voltage/current mode controls.Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.Proficient Level in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.Excellent scripting and automation skills using TCL, Python or C/C++.Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.Good written/verbal communication skills and strong teamwork/collaboration.Knowledge/Experience with the following is a plus: automotive standards/FuSA, I2C, I3C, SPI, USB, PMBUS, I2S, CAN, LIN, Embedded MCU(ARM/RISC V) designs and/or SoC development.Ability to communicate in Chinese highly desired.Location:

San Jose, CAMPS offers a comprehensive benefits package. We provide health care coverage, dental and vision, 401(K), Employee Stock Purchase Program (ESPP), up to 11 company paid holidays, and 15-20 days of paid time off depending on your tenure, generous discretionary company bonuses, and life and disability protection. Employees in sales positions may be eligible for our sales incentive bonuses. Employees in certain positions may be eligible for stock compensation. For more information on MPS’ benefits please view our company website at www.monolithicpower.com.Pay is based on market location and may vary based on factors including experience, skills, education and other job-related reasons. The base salary range for this position in California is $180,000 - $230,000.

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