Cadence Design Systems
Sr. Principal EDA Software Engineer (C+, Characterization)
Cadence Design Systems, San Jose, California, United States, 95199
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets.Must haves:
8+ years of experience in development of EDA tools and one or more of transistor level timing, power, noise, aging, reliability, and emir analysisHardcore C++ Knowledge – LinuxProficiency designing data structures, algorithms, and software engineering principlesIndustry experience developing and maintaining C++ based applications on a Unix or Linux environmentRequirements:
Experience with quality and software processesProficiency in analyzing transistor or gate level schematicsThe preferred candidate is expected to have a BS in CS/EE/CENice to haves:
Experience in development of circuit simulation or library characterization programsHigh level understanding of SPICE simulation transistor modelsExperience with distributed programming, database design, and cloud APIs for distributed computingYour work will be focused on:
Enhancing and expanding the existing tools' architecture to cover timing analysisCreating new frameworks for analysis of effects dominant at n5 and belowUsing machine learning technology to bring order of magnitude speed / capacity / usability improvements over existing solutionsThe annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.We’re doing work that matters. Help us solve what others can’t.
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8+ years of experience in development of EDA tools and one or more of transistor level timing, power, noise, aging, reliability, and emir analysisHardcore C++ Knowledge – LinuxProficiency designing data structures, algorithms, and software engineering principlesIndustry experience developing and maintaining C++ based applications on a Unix or Linux environmentRequirements:
Experience with quality and software processesProficiency in analyzing transistor or gate level schematicsThe preferred candidate is expected to have a BS in CS/EE/CENice to haves:
Experience in development of circuit simulation or library characterization programsHigh level understanding of SPICE simulation transistor modelsExperience with distributed programming, database design, and cloud APIs for distributed computingYour work will be focused on:
Enhancing and expanding the existing tools' architecture to cover timing analysisCreating new frameworks for analysis of effects dominant at n5 and belowUsing machine learning technology to bring order of magnitude speed / capacity / usability improvements over existing solutionsThe annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.We’re doing work that matters. Help us solve what others can’t.
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