Analog Devices, Inc.
Sr. Principal – Digital Design Lead
Analog Devices, Inc., Sioux Falls, South Dakota, United States,
Sr. Principal – Digital Design Lead
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.Description:The Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced
Digital Design Lead
who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.A key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.Job Responsibilities:Provide technical leadership and expertise to a team of design engineers on all aspects of digital design & quality assurance
(CDC, Low Power design, Synthesis & timing closure, Design for Test improvements, silicon debug etc)Architect and Design
key digital blocks
such as accelerators/ data path IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffsDemonstrate strong understanding of heterogenous processor cores & subsystems
(A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirementsWork closely with all stakeholders, including product teams, project managers, senior managers & leadership team to align team schedules, milestones, commitments, deliverablesConduct detail-oriented design reviews
and drive adherence to quality metricsCreate and manage a streamlined workflow for the design team that enables them to work collaboratively and efficiently. This includes creating a project visibility system and setting up design review processes to establish a clear scheme of design deliveryDrive efforts towards development of Design Management and IP Centric infrastructure and flows
across different tools such as Methodics / Perforce / Github / IP catalog creation etcDevelop and maintain catalog of digital IPs
to enable ease of information sharing to customers across different BUsLead the way to build deep expertise on complex interfaces , peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2DPackage Digital IP for seamless integration
into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc.Drive evaluation of 3rd party IPs
on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendationsEstablish evaluation flows
for home-grown & 3rd party IPs for consistent benchmarking of evaluationManage & streamline efforts towards consolidation/ curation of digital IP blocks, such as standard peripherals, processor cores & collaterals, high speed protocol & interface IPStrive to remove complexity and ambiguity within the teams and their processes. Ability to distil and provide clear and actionable recommendations to the teamPosition Requirements :Minimum B.E. /B. Tech degree in Electrical/Electronics/Computer science15+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-VerilogStrong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspectsProven experience in managing/ handling large complex hardware projects in lead roleStrong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutionsExperience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design qualityStrong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power designExperience with developing timing constraints and ability to carry out logic synthesis and Static timing analysisAbility to technically mentor a large digital design teamGood interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographicallyStrong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocolsKnowledge of Processor/SoC architecture and/or DSP fundamentalsServe as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary.
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Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.Description:The Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced
Digital Design Lead
who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.A key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.Job Responsibilities:Provide technical leadership and expertise to a team of design engineers on all aspects of digital design & quality assurance
(CDC, Low Power design, Synthesis & timing closure, Design for Test improvements, silicon debug etc)Architect and Design
key digital blocks
such as accelerators/ data path IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffsDemonstrate strong understanding of heterogenous processor cores & subsystems
(A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirementsWork closely with all stakeholders, including product teams, project managers, senior managers & leadership team to align team schedules, milestones, commitments, deliverablesConduct detail-oriented design reviews
and drive adherence to quality metricsCreate and manage a streamlined workflow for the design team that enables them to work collaboratively and efficiently. This includes creating a project visibility system and setting up design review processes to establish a clear scheme of design deliveryDrive efforts towards development of Design Management and IP Centric infrastructure and flows
across different tools such as Methodics / Perforce / Github / IP catalog creation etcDevelop and maintain catalog of digital IPs
to enable ease of information sharing to customers across different BUsLead the way to build deep expertise on complex interfaces , peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2DPackage Digital IP for seamless integration
into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc.Drive evaluation of 3rd party IPs
on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendationsEstablish evaluation flows
for home-grown & 3rd party IPs for consistent benchmarking of evaluationManage & streamline efforts towards consolidation/ curation of digital IP blocks, such as standard peripherals, processor cores & collaterals, high speed protocol & interface IPStrive to remove complexity and ambiguity within the teams and their processes. Ability to distil and provide clear and actionable recommendations to the teamPosition Requirements :Minimum B.E. /B. Tech degree in Electrical/Electronics/Computer science15+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-VerilogStrong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspectsProven experience in managing/ handling large complex hardware projects in lead roleStrong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutionsExperience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design qualityStrong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power designExperience with developing timing constraints and ability to carry out logic synthesis and Static timing analysisAbility to technically mentor a large digital design teamGood interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographicallyStrong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocolsKnowledge of Processor/SoC architecture and/or DSP fundamentalsServe as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary.
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