Sr. ASIC Design Engineer

This is an onsite position, employees are expected to work from our Redwood City office

The Role:

• Design and develop high-performance, synthesizable RTL code using SystemVerilog, Verilog or VHDL
• Participate in microarchitecture definition and refinement
• Implement and optimize logic for specific functionalities and performance targets
• Conduct functional verification through simulations and formal methods
• Collaborate with architects, verification engineers, and physical designers to ensure successful integration and production
• Write clear and concise technical documentation
• Stay up-to-date with the latest advancements in digital design technologies and methodologies

Skills & Qualifications:

• Bachelor's or Master’s degree in Computer Science, Electrical Engineering, or a related field
• Minimum 2+ years of experience (will consider bright individuals even with lower experience) in RTL design and verification
• Proven expertise in SystemVerilog, Verilog or VHDL
• Strong understanding of computer architecture
• Familiarity with synthesis and timing constraints
• Knowledge of programming languages: Python, C, C++. Tcl, shell scripting, CUDA C++ are a plus.
• Excellent written and verbal communication skills
• Strong ability to work independently and as part of a team

About Vorticity

As passionate scientists and engineers, we are well aware of the plethora of critical problems in the world that cannot be solved because humanity simply does not have enough computing power. To address this, Vorticity is developing a radically new silicon chip architecture and system to dramatically accelerate scientific computing problems.

Vorticity’s mission is to expand human ingenuity. To do that we are building a team of exceptional people to work together on big problems. Join us!