Amazon
ASIC Design Engineer, Hardware Compute Group
Amazon, Sunnyvale, California, United States, 94087
ASIC Design Engineer, Hardware Compute Group
As a ASIC Design Engineer, you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop hardware IP to accelerate applications in machine learning, computer vision and robotics. You will work closely with scientists, SoC Architects, software and verification to develop IP that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for design and implementation of large complex IP blocks.In this role you will:Micro-architect and design hardware accelerator IP in Verilog HDLHelp define and own ASIC design methodologiesLead cross functional SOC development activitiesWork with the different stakeholders and functional teams to ensure delivery of high quality IP to SoC product teamsProvide technical leadership through personal example, mentorship, and strong teamworkBASIC QUALIFICATIONS
BS degree or higher in EE or CE or CS5+ years or more of practical semiconductor ASIC design experience including owning end to end design of major SOC blocksSuccessful tape outs as an owner of a major design blockExperience writing HDL in Verilog/SystemVerilog and understanding architectural models and algorithms in C/C++Proficient in design methodologies and EDA toolsExperience working with Synthesis, timing and design constraintsPREFERRED QUALIFICATIONS
In-depth knowledge of CPU, DSP, or programmable acceleratorsExperience working with RISC-VSOC bring-up and post silicon validation experienceExperience with early power analysisArchitecture/System engineering experienceExperience developing with modern programming languages (Python, Java, C/C++), open-source technologies, and LinuxExperience with gate level testing and multi clock design practices (CDC)Experience working with software teams to tightly define the HW/SW interface including control/status registers, and error handlingExperience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and areaExperience in micro-architecture definition from architecture guideline and model analysisExperience in RTL coding and debug, as well as performance/power/area analysis and trade-offsExperience in timing analysis and working with physical design teams to close timingExperience in working with internal and external partners
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As a ASIC Design Engineer, you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop hardware IP to accelerate applications in machine learning, computer vision and robotics. You will work closely with scientists, SoC Architects, software and verification to develop IP that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for design and implementation of large complex IP blocks.In this role you will:Micro-architect and design hardware accelerator IP in Verilog HDLHelp define and own ASIC design methodologiesLead cross functional SOC development activitiesWork with the different stakeholders and functional teams to ensure delivery of high quality IP to SoC product teamsProvide technical leadership through personal example, mentorship, and strong teamworkBASIC QUALIFICATIONS
BS degree or higher in EE or CE or CS5+ years or more of practical semiconductor ASIC design experience including owning end to end design of major SOC blocksSuccessful tape outs as an owner of a major design blockExperience writing HDL in Verilog/SystemVerilog and understanding architectural models and algorithms in C/C++Proficient in design methodologies and EDA toolsExperience working with Synthesis, timing and design constraintsPREFERRED QUALIFICATIONS
In-depth knowledge of CPU, DSP, or programmable acceleratorsExperience working with RISC-VSOC bring-up and post silicon validation experienceExperience with early power analysisArchitecture/System engineering experienceExperience developing with modern programming languages (Python, Java, C/C++), open-source technologies, and LinuxExperience with gate level testing and multi clock design practices (CDC)Experience working with software teams to tightly define the HW/SW interface including control/status registers, and error handlingExperience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and areaExperience in micro-architecture definition from architecture guideline and model analysisExperience in RTL coding and debug, as well as performance/power/area analysis and trade-offsExperience in timing analysis and working with physical design teams to close timingExperience in working with internal and external partners
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